Pipeline design for car assembly line is a method of systematically dividing the combinational logic, inserting registers between various parts (levels), and temporarily storing intermediate data.

The purpose is to increase the data throughput rate (increase the processing speed). The pipeline shortens the path length that the signal given in one clock cycle must pass, thereby increasing the clock frequency. For example: a 2-level combinational logic, assuming that the delay of each level is the same as Tpd.

1. The total delay without pipeline is 2Tpd, which can be completed in one clock cycle, but the clock cycle is limited to 2Tpd;
2. Pipeline: After each stage is added to the register (the delay is Tco), the single-stage delay is Tpd+Tco, and each stage consumes one clock cycle. The pipeline needs 2 clock cycles to obtain the first calculation result, which is called the first delay , It needs 2*(Tpd+Tco), but when performing repeated operations, only one clock cycle is required to obtain the final calculation result, which is called throughput delay (Tpd+Tco); it can be seen that as long as Tco is less than Tpd, the pipeline can increase the speed. Corollary: Increasing the length of the pipeline can save more delay. The longer the pipeline, the greater the first delay. If the pipeline is started repeatedly, it will lose speed.

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